(1) Field of the Invention
The present invention relates to a static induction thyristor, and more especially to a static induction thyristor comprising a first high concentration layer provided at one surface of a semiconductor layer, a second high concentration layer provided at the other surface of said semiconductor layer, a buried region provided in the semiconductor layer, a cathode electrode provided on said surface, and an anode electrode provided on the other surface.
(2) Description of the Prior Art
Before explaining the static induction thyristor of the present invention, explanation for the already disclosed static induction thyristor having the buried gates will be given by referring to FIGS. 1-3.
FIG. 1 is a schematic cross-sectional view for showing a static induction thyristor having conventional buried gate construction and FIG. 2 is a simplified equivalent circuit diagram of the thyristor shown in FIG. 1.
In FIG. 1, the reference numeral 1 generally indicates a static induction thyristor comprising a first high concentration layer, for instance, an n.sup.+ layer 4 provided on the side of one surface 3 of a semiconductor layer 2 of n type for instance, a second high concentration layer, for instance, a p.sup.+ layer 6 provided on the side of the other surface 5, a gate region 7 provided on the side of the surface 3 of said semiconductor layer 2 and buried gate regions 8 embedded in the semiconductor layer 2. The both gate regions 7 and 8 together function as the gate. The region 7 and the buired gate regions 8 are both formed by diffusion method. Further a cathode electrode 9 is provided on the first high concentration layer 4, an anode electrode 10 is provided below the second high concentration layer 6 and a gate electrode 11 is provided on the gate region 7. These electrodes can be formed by aluminium for instance. A supporting electrode 12 is provided below the anode electrode 10 and these two parts together act as the anode.
Device construction along line A--A is the conventional thyristor of p-n-p-n 4 layer structure and that along line B--B is a diode part having p.sup.+ -n-n.sup.+ structure.
The equivalent circuit diagram of this kind of thyristor is schematically shown in FIG. 2. As can be seen from the equivalent circuit diagram, it comprises a p-n-p transistor T.sub.1 and an n-channel static induction transistor T.sub.2 of which source S is connected to the cathode electrode 9, gate G is connected to the gate electrode 11, and drain D is connected to base B of the transistor T.sub.1 and the emitter E of the transistor T.sub.1 is connected to the anode electrode 10.
Considering the respective regions of the device shown in FIG. 1 and the elements shown in FIG. 2, it is to be noted that the emitter E corresponds to the second high concentration layer (p.sup.+ layer) 6, the base B and the drain D correspond to the substrate (n-layer) 2a, the collector C and the gate G correspond to the gate regions 7 and 8 and the source S corresponds to the first high concentration layer (n.sup.+ layer) 4. As can be understood clearly from FIG. 2, the illustrated thyristor 1 comprises a series connection of a p-n-p transistor T.sub.1 and a static induction transistor (which may be abridged as SI transistor) T.sub.2 having no amplifying function. Accordingly, this static induction thryristor 1 has a higher dv/dt capacity at immediate after the turn-off compared with a conventional p-n-p-n four layer structure thyristor basically having a series connection of a p-n-p transistor having a current amplifying function and an n-p-n transistor.
However, in practically manufacturing the thyristor having construction as shown in FIG. 1, the p.sup.+ gate regions 7 and 8 are formed on the n type substrate 2a by diffusion method and thereafter an arrangement is made to bury the formed p.sup.+ gate regions 8. Namely, an n type epitaxial layer 2b is grown on the substrate 2a and the semiconductor layer 2 is formed and the thyristor is manufactured. Between the channel area of the thyristor and the gate area of said thyristor there is the following relation; EQU channel area&lt;&lt;gate area
In a practical embodiment, the gate area is 6-10 times larger compared with the channel area. Since the gate and the channel are in the above relation for the size of the area, the equivalent circuit diagram of the static induction thyristor shown in FIG. 1 will not be a simple one as shown in FIG. 2 but it behaves as a diagram as shown in FIG. 3, in which the static induction transistor T.sub.2 is connected with a parasitic n-p-n transistor T.sub.3. Namely, the parasitic n-p-n transistor T.sub.3 having a large gate area and having current amplifying function is connected in parallel with the static induction transistor T.sub.2 essentially having no current amplifying function. By this reason, there had been a trouble that by the charging current for charging the static capacity of the depletion layer caused by the re-applied voltage between the anode and the cathode after the rupturing of the main current, the parasitic n-p-n transistor T.sub.3 might become ON condition and the static induction thyristor may be turn-off failure. By this cause of trouble, the static induction thyristor having construction shown in FIG. 1 has a drawback in that the dv/dt capability immediately after the turn-off can not be so large as expected.
This cause is further considered by referring to FIGS. 4 and 5.
As can be seen from FIG. 4, when the p.sup.+ gate regions 8 are formed by the diffusion method, p type impurity boron, which has masking effect against an oxide film and resulting a high surface concentration is selectively diffused through windows 14 provided in the oxide film 13. The boron atoms diffused from the window having width (W) are distributed into the silicon substrate body from the point Z located at bottom surface of the window 14 along X and Y axes in accordance with the diffusion equation. The concentration distribution of boron shows a sudden decrease according to an exponential function or error function according to an increase of distance from the point Z along the X and Y axes. It is preferred to raise the surface concentration of boron at the point Z since it results a smaller gate resistance of the static induction thyristor and a shorter gate turn-off time. On the other hand, boron has relatively small atomic radius which is 74% of that of silicon so if the diffusion is made at the surface concentration in an order of 10.sup.19 atoms/cc and in the depth of 15-20 .mu.m, crystal defects might be caused in the surface of the silicon substrate (of the order of 10.sup.13 atoms/cc). Accordingly, a high quality epitaxial layer can not be obtaind by epitaxial growth of n-type silicon single-crystal in an order of 10.sup.14 -10.sup.15 atoms/cc on the p.sup.+ gate surface having such defects so that yields of manufacture deteriorates. By the above reason, the surface concentration at the point Z of the gate region 8 is limited and its possible range in the present industry is 5.times.10.sup.17 .about.5.times.10.sup.18 atoms/cc.
When the surface concentration of the point Z is made 1.times.10.sup.18 atoms/cc and the depth of p gate (in X axis) is made 20 .mu.m, the diffusion in the direction of Y axis is 14 .mu.m. The distances viewed from the point Z to points along X and Y axes to points at which the concentration decreases down to 6.about.8.times.10.sup.16 atoms/cc are at least 13 .mu.m and 10 .mu.m, respectively. There is formed a depletion layer 15 as shown in the drawing (FIG. 5). Accordingly, the p.sup.+ gate region 8 has a construction of p.sup.+ -n-p-n.sup.+ as indicated by arrows and current will flow for charging up the depletion layer 15. This is the region to operate as the conventional 4 layer construction thyristor. If the boron concentration is more than about value of 1.times.10.sup.17 atoms/cc along X and Y axes, the function of the conventional 4 layer construction thyristor is not achieved as is known empirically. By the aforementioned reason, in the static induction thyristor formed by the gate diffusion method having construction shown in FIG. 1, there is a region having the same function with the conventional p-n-p-n 4 layer construction thyristor about cross-section around the gate along the line A--A. This region is very important and can not be ignored since the following relationship exists for the static induction thyristor. EQU channel area&lt;&lt;gate area
Due to this fact, the equivalent electric circuit diagram of FIG. 3 is considered and in which n-p-n transistor operation prevails and the essentially high dv/dt capability of the static induction thyristor is not achieved.
Furthermore, in a static induction thyristor of buried gate construction having p-gates formed by diffusion method, the gate electrodes are formed from the buried gates, the epitaxial grown layer formed over the gate surface should be removed by dry or wet etching process. In this occasion, if the etching is applied to a depth exceeding the thickness of the epitaxial layer, the blocking voltage between the anode and the gates may remarkably decrease from an intended design value and this may causes problem.
The cause of this will be explained by referring to FIG. 6.
In order to form the gate electrodes as shown in FIG. 6, it is necessary to apply a working to remove up to depth l which substantially corresponds to the thickness of the epitaxial layer. Thus disposed gate surface is applied with an aluminium electrode. In this case, according to an increase of removing depth l of the gate and an increase of the thickness of the epitaxially grown layer, an over-etching d' is resulted in the following relationship. EQU amount of over-etching (d')=removing depth (l)- thickness of epitaxial layer (d)
By this the blocking voltage between the anode and the gate decreases. This reason is considered from the followings. When the reverse voltage is applied to the gate junction, the depletion region 15 bearing said reverse voltage mainly expands towards n-layer side, but a small part thereof also expands towards p.sup.+ side of the gate layer. Accordingly, if the amount of the over-etching (d') increases, the depletion layer 15 expanded towards p.sup.+ gate side may reach the gate electrode. From this, the voltage bearing facility of the gate junction is disturbed and the blocking voltage between the anode and the gate thus decreases. The main cause for this is a sudden variation of the concentration from point Z (refer to FIG. 4) in the formation of the gate by the diffusion method.
Herein, the relation between the anode-gate blocking voltage V.sub.AG and the etching amount l at the time of removal is shown in FIG. 7. As can be seen therefrom, for obtaining the intended anode-gate blocking voltage V.sub.AG, the over-etching amount d' should be limited within a few .mu.m. However, it is a difficult problem to limit the over-etching amount d' within a few .mu.m against the thickness of the epitaxial layer of 15-20 .mu.m. This will be a big bar at an attempt to enlarge the surface area of the element. On the contrary, if the etching amount l is insufficient at the time of exposing the gate electrodes, i.e. when the p-gate surface is not exposed, a problem exists in that the gate-cathode blocking voltage can not be maintained due to the fact that the gate and the cathode are short-circuited by the n-layer.
If we can realize a construction having no concentration variation along the X-axis, the problems explained above may not occur. Further, there is another problem relating to the over-etching amount d' and this is the gate resistance. The gate resistance mainly depends on the etching distance viewed from the point Z. This means a fact that the concentration distribution along X-axis varies suddenly at said point Z. Namely, the gate resistance becomes high according to an increase of the over-etching amount. In a static induction thyristor having a definite channel interval, the turn-off time Tq increases according to an increase of the gate resistance as can be seen from an experimental data shown in FIG. 8.
FIG. 8 shows a relation between the gate resistance Rg and the turn-off time Tq at the time of turn-off.
Namely, many samples having low gate resistance Rg have much shorter gate turn-off time. Whereas those having high gate resistance Rg may have longer gate turn-off time Tq.
From this fact, it can be said that the undue increase of the etching amount is undesirable since it causes an increase of the gate turn-off time of the static induction thyristor. The main reason for this is that the gates are formed through diffusion method and the concentration distribution from Z-axis shows sudden variation. If it can be realized a construction in which the concentration distribution of the gate along X-axis shows no variation, the aforementioned problem will not happen.
Furthermore, when we consider a case in which gate is positively biassed for turn-on a thyristor, there is a p.sup.+ -n-n.sup.+ diode between the gate and the cathode of the thyristor since there is a high concentration layer (n.sup.+ layer) on the top of the buried gate region 8 buried in the semiconductor layer 2. By this reason, there has been a drawback in that the gate loss (gate turn-on current) is large at high frequency operation.
Still further, if the epitaxial growing is applied over a substrate of a large surface area, defects may be involved in the epitaxial growing layer. In such a defect portion, the diffusion speed of n.sup.+ impurity atom is high and the diffusion is spread in a more deep place. Therefore, a disadvantage for lowering cathode-gate blocking voltage is caused by the short circuit of p.sup.+ buried gate regions. This may result decrease of manufacturing yield of thyristors.
Furthermore, when we consider a case in which the gates are positively biassed for turn-on the thyristor, it can be assumed that a p.sup.+ -n-n.sup.+ diode is present between the gate and cathode of the thyristor since there is a high concentration layer (n.sup.+ layer) directly above the buried gate region 8 embedded in the semi-conductor region. By this reason, there has been a disadvantage in that the gate loss or the gate turn-on current is large at the turn-on in a high frequency operation.
Moreover, if the abovementioned epitaxial growing is applied on a large area substrate, the epitaxially grown layer may have defect portions. In such a defect portion, the diffusion speed of n.sup.+ impurity atom is high compared with non-defect portion so that the diffusion is effected at higher speed to deeper portion. Accordingly, there is a disadvantage in that the gate-cathode blocking voltage of the thyristor may be lowered by causing short-circuit of the buried gate regions. This may be one cause of lowering the manufacturing yield of the thyristor.